1. Field of the Invention
The present invention relates to main memory systems for computer systems, and more specifically to supporting multiple memory ranks per channel.
2. Background of the Related Art
Memory modules, such as dual in-line memory modules (DIMMs), include one or more ranks of memory. A rank is a subset of memory chips that can be accessed on a DIMM. The number of ranks on a DIMM, or the number of ranks collectively provided on a memory channel having one or more DIMMs, is the number of independent sets of DRAMs that can be accessed for the full data bit-width of the DIMM, which is typically 64 bits plus eight optional ECC (error correcting code) bits. The main memory bus typically includes a number of read/write data lines (e.g. an I/O data path) corresponding to the data bit-width of each rank of DIMMs on the memory channel. Two ranks cannot be accessed simultaneously because each rank shares the same data path provided by the memory bus. Therefore, the main memory bus also includes chip select (CS) lines to select which rank of memory receive and respond to commands at any given moment.
In a conventional memory system, each CS line is uniquely associated with a different rank on a memory channel. A rank is accessed by activating the CS line with which it is associated. For example, a memory channel having two quad-rank DIMMs, totaling eight ranks on the memory channel, may be allocated eight CS lines on the memory bus, with each CS line designating one of the eight ranks. CS lines are usually “active low,” meaning that a CS line is active at the lower of two voltages, corresponding to a binary “0.” Assuming the currently active CS line is active low, the remaining CS lines are each driven “high,” as a binary “1” to inactivate the other ranks on the shared bus.
To support the development of quad-rank DIMM, which currently remains in common use, the standard pinout for both DDR2 and DDR3 DIMMs include pins for four CS lines to be routed through the socket to the DIMM. A memory controller having eight CS pins can be used to control two quad-rank DIMMs per channel, with four of the CS pins designating four ranks of one DIMM and the other four CS pins designating four ranks of the other DIMM.